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| specifications subject to change with out notice,contact your sales represent atives for the most recent information. 1/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 features 2.4v ~ 3.0v for v version working voltage: 3.0v ~ 3.6v for l version 4.5v ~ 5.5v for c version general 8052 family compatible 12 clocks per machine cycle 64k byte on chip program flash 4096 byte on-chip data ram three 16 bit timers/counters one watch dog timer four 8-bit i/o ports for pdip package four 8-bit i/o ports + one 4-bit i/o ports for plcc or qfp package full duplex serial channel bit operation instruction industrial level 8-bit unsigned division 8-bit unsigned multiply bcd arithmetic direct addressing indirect addressing nested interrupt two priority level interrupt a serial i/o port power save modes: idle mode and power down mode code protection function low emi (inhibit ale) bank mapping direct addressing mode for access on-chip ram 8 channel pwm function with p1.0 ~ p1.7 postfix package pin/pad configuration dimension p 40l pdip page 2 page 21 j 44l plcc page 2 page 22 q 44l qfp page 2 page 23 product list sm79164v16j/q,16mhz 64kb internal flash mcu sm79164l20p, 20mhz 64kb internal flash mcu sm79164l25j/q, 25mhz 64kb internal flash mcu sm79164c25p, 25mhz 64kb internal flash mcu SM79164C35J/q, 35mhz 64kb internal flash mcu description the sm79164 series product is an 8 - bit single chip micro controller with 64kb on-chip flash and 4k byte ram embedded. it is a derivative of the 8052 micro controller family. it has 8-channel pwm build-in. user can access on-chip expanded ram with easier and faster way by its ?bank mapping direct addressing mode? scheme. with its hardware features and powerful instruction set, it?s straight forward to make it a versatile and cost effective controller for those applicat ions which demand up to 32 i/o pins for pdip package or up to 36 i/o pins for plcc/qfp package, or applications which need up to 64k byte flash memory for program data. to program the on-chip flash memory, a commercial writer is available to do it in parallel programming method. ordering information yywwv sm79164ihhkl yy: year, ww:month v: version identifier {, a, b,...} i:process identifier {v=2.4v~ 3.0v, l=3.0v ~ 3.6v, c=4.5v ~ 5.5v} hh: working clock in mhz {20, 25, 35} k: package type postfix {as below table} l:pb free identifier no text is non- pb free ,?p? is pb free taiwan 6f, no. 10-2 li - hsinchu first road , science-based industrial park, hsinchu, taiwan 30078 tel: 886-3-5671820 886-3-5671880 fax: 886-3-5671891 886-3-5671894 8 - bit micro-controller web site: http://www.syncmos.com.tw with 64kb flash & 4kb ram embedded
specifications subject to change with out notice,contact your sales represent atives for the most recent information. 2/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 pin configurations ad3/p0.3 ad2/p0.2 ad1/p0.1 ad0/p0.0 vdd p4.2 t2/pwm0/p1.0 t2ex/pwm1/p1.1 pwm2/p1.2 pwm3/p1.3 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 p4.0 vss xtal1 xtal2 p3.7/#rd p3.6/#wr p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 #ea p4.1 ale #psen p2.7/a15 p2.6/a14 p2.5/a13 pwm5/p1.5 pwm6/p1.6 pwm7/p1.7 res rxd/p3.0 p4.3 txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 sm79164 44l qfp (top view) 33 32 31 30 27 26 25 24 23 29 28 22 21 20 18 17 16 15 14 13 19 12 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 sm79164ihhp (top view ) 40l pdip vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 #ea ale #psen p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 pwm0/t2/p1.0 pwm1/t2ex/p1.1 pwm2/p1.2 pwm3/p1.3 pwm4/p1.4 pwm5/p1.5 pwm6/p1.6 pwm7/p1.7 res rxd/p3.0 txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 #wr/p3.6 #rd/p3.7 xtal1 xtal2 vss 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 10 40 39 38 37 36 35 34 33 32 31 30 28 27 26 25 24 23 22 21 29 p1.4/pwm4 p1.3/pwm3 p1.2/pwm2 p1.1/t2ex/pwm1 p1.0/t2/pwm0 p4.2 vdd p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 #ea p4.1 ale #psen p2.7/a15 p2.6/a14 p2.5/a13 pwm5/p1.5 pwm6/p1.6 pwm7/p1.7 res rxd/p3.0 p4.3 txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 sm79164 44l plcc (top view) 6 5 4 3 2 14443 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 #wr/p3.6 #rd/p3.7 xtal2 xtal1 vss p4.0 a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 pwm4/p1.4 ihhj ihhq specifications subject to change with out notice,contact your sales represent atives for the most recent information. 3/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 timer 2 timer 1 timer 0 stack pointer decoder & register 4096 bytes ram block diagram reset circuit power circuit interrupt circuit timing generator xtal2 xtal1 #ea ale #psen res vdd vss to pertinent blocks to whole chip to pertinent blocks to whole system acc buffer2 buffer1 alu psw buffer dptr pc incrementer program counter register port 1 latch port 2 latch port 3 latch port 4 latch port 2 port 3 driver & mux port 4 driver & mux 8 8 8 4 wdt instruction register port 0 latch 8 port 1 driver & mux driver & mux port 0 driver & mux pwm 64k bytes flash memory 0000h ffffh 8 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 4/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 pin descriptions 40l pdip pin# 44l qfp pin# 44l plcc pin# symbol active i/o names 1 40 2 p1.0/t2/pwm0 i/o bit 0 of port 1 & timer 2 clock out , pwm channel 0 2 41 3 p1.1/t2ex/pwm1 i/o bit 1 of port 1 & timer 2 control , pwm channel 1 3 42 4 p1.2/pwm2 i/o bit 2 of port 1 & pwm channel 2 4 43 5 p1.3/pwm3 i/o bit 3 of port 1 & pwm channel 3 5 44 6 p1.4/pwm4 i/o bit 4 of port 1 & pwm channel 4 6 1 7 p1.5/pwm5 i/o bit 5 of port 1 & pwm channel 5 7 2 8 p1.6/pwm6 i/o bit 6 of port 1 & pwm channel 6 8 3 9 p1.7/pwm7 i/o bit 7 of port 1 & pwm channel 7 9 4 10 res h i reset 10 5 11 p3.0/rxd i/o bit 0 of port 3 & receive data 11 7 13 p3.1/txd i/o bit 1 of port 3 & transmit data 12 8 14 p3.2/#int0 l/ - i/o bit 2 of port 3 & low true interrupt 0 13 9 15 p3.3/#int1 l/ - i/o bit 3 of port 3 & low true interrupt 1 14 10 16 p3.4/t0 i/o bit 4 of port 3 & timer 0 15 11 17 p3.5/t1 i/o bit 5 of port 3 & timer 1 16 12 18 p3.6/#wr i/o bit 6 of port 3 & ext. memory write 17 13 19 p3.7/#rd i/o bit 7 of port 3 & ext. mem. read 18 14 20 xtal2 o crystal out 19 15 21 xtal1 i crystal in 20 16 22 vss sink voltage, ground 21 18 24 p2.0/a8 i/o bit 0 of port 2 & bit 8 of ext. memory address 22 19 25 p2.1/a9 i/o bit 1 of port 2 & bit 9 of ext. memory address 23 20 26 p2.2/a10 i/o bit 2 of port 2 & bit 10 of ext. memory address 24 21 27 p2.3/a11 i/o bit 3 of port 2 & bit 11 of ext. memory address 25 22 28 p2.4/a12 i/o bit 4 of port 2 & bit 12 of ext. memory address 26 23 29 p2.5/a13 i/o bit 5 of port 2 & bit 13 of ext. memory address 27 24 30 p2.6/a14 i/o bit 6 of port 2 & bit 14 of ext. memory address 28 25 31 p2.7/a15 i/o bit 7 of port 2 & bit 15 of ext. memory address 29 26 32 #psen o program storage enable 30 27 33 ale o address latch enable 31 29 35 #ea l i external access 32 30 36 p0.7/ad7 i/o bit 7 of port 0 & data/address bit 7 of ext. memory 33 31 37 p0.6/ad6 i/o bit 6 of port 0 & data/address bit 6 of ext. memory 34 32 38 p0.5/ad5 i/o bit 5 of port 0 & data/address bit 5 of ext. memory 35 33 39 p0.4/ad4 i/o bit 4 of port 0 & data/address bit 4 of ext. memory 36 34 40 p0.3/ad3 i/o bit 3 of port 0 & data/address bit 3 of ext. memory 37 35 41 p0.2/ad2 i/o bit 2 of port 0 & data/address bit 2 of ext. memory 38 36 42 p0.1/ad1 i/o bit 1 of port 0 & data/address bit 1 of ext. memory 39 37 43 p0.0/ad0 i/o bit 0 of port 0 & data/address bit 0 of ext. memory 40 38 44 vdd drive voltage, +5 vcc 17 23 p4.0 i/o bit 0 of port 4 28 34 p4.1 i/o bit 1 of port 4 39 1 p4.2 i/o bit 2 of port 4 6 12 p4.3 i/o bit 3 of port 4 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 5/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 special function regist er (sfr) memory map b acc p4 pwmc4 pwmc5 pwmc6 pwmc7 psw pwmc0 pwmc1 pwmc2 pwmc3 t2con t2mod rcap2l rcap2h tl2 th2 ip pwmd4 pwmd5 pwmd6 pwmd7 sconf p3 pwmd0 pwmd1 pwmd2 pwmd3 ie p2 scon sbuf p1con wdtc p1 wdtket tcon tmod tl0 tl1 th0 th1 p0 sp dpl dph (reserved) rcon dbank pcon $f8 $f0 $e8 $e0 $d8 $d0 $c8 $c0 $b8 $b0 $a8 $a0 $98 $90 $88 $80 $ff $f7 $ef $e7 $df $d7 $cf $c7 $bf $b7 $af $a7 $9f $97 $8f $87 note: the text of sfrs with bold type characters are extension special function registers for sm79164 addr sfr reset 7 6 5 4 3 2 1 0 85h rcon 00h rams3 rams2 rams1 rams0 86h dbank 0*000001 bse bs5 bs4 bs3 bs2 bs1 bs0 97h wdtkey 00h wdtkey7 wdtkey6 wdtkey5 wdtkey4 wdtkey3 wdtkey2 wdtkey1 wdtkey0 9bh p1con 00h pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 9fh wdtc 0*0**000 wdte reserve clear ps2 ps1 ps0 b3h pwmd0 00h pwmd07 pwmd06 pwmd05 pwmd04 pwmd03 pwmd02 pwmd01 pwmd00 b4h pwmd1 00h pwmd17 pwmd16 pwmd15 pwmd 14 pwmd13 pwmd12 pwmd11 pwmd10 b5h pwmd2 00h pwmd27 pwmd26 pwmd25 pwmd24 pwmd23 pwmd22 pwmd21 pwmd20 b6h pwmd3 00h pwmd37 pwmd36 pwmd35 pwmd34 pwmd33 pwmd32 pwmd31 pwmd30 bbh pwmd4 00h pwmd47 pwmd46 pwmd45 pwmd44 pwmd43 pwmd42 pwmd41 pwmd40 bch pwmd5 00h pwmd57 pwmd56 pwmd55 pwmd54 pwmd53 pwmd52 pwmd51 pwmd50 bdh pwmd6 00h pwmd67 pwmd66 pwmd65 pwmd64 pwmd63 pwmd62 pwmd61 pwmd60 beh pwmd7 00h pwmd77 pwmd76 pwmd75 pwmd74 pwmd73 pwmd72 pwmd71 pwmd70 special function register (sfr) the address $80 to $ff can be accessed by direct addressing mode only. address $80 to $ff is sfr area. the following table lists the sfrs which are identical to general 8052, as well as sm79164 extension sfrs. specifications subject to change with out notice,contact your sales represent atives for the most recent information. 6/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 addr sfr reset 7 6 5 4 3 2 1 0 bfh sconf 0*****00 wdr ome alei c8h t2con 00h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 c9h t2mod ******00 t2oe dcen d3h pwmc0 *****000 pbs0 pfs01 pfs00 d4h pwmc1 *****000 pbs1 pfs11 pfs10 d5h pwmc2 *****000 pbs2 pfs21 pfs20 d6h pwmc3 *****000 pbs3 pfs31 psf30 dbh pwmc4 *****000 pbs4 pfs41 pfs40 dch pwmc5 *****000 pbs5 pfs51 pfs50 ddh pwmc6 *****000 pbs6 pfs61 pfs60 deh pwmc7 *****000 pbs7 pfs71 psf70 d8h p4 ****1111 p4.3 p4.2 p4.1 p4.0 extension function description 1. memory structure the sm79164 is the general 8052 hardware core as a single chip micro controller. its memory structure follows general 8052 structure. 1.1 program memory the sm79164 has 64k byte on-chip flash memory which used as general program memory. the address range for the 64k byte is $0000 to $ffff. 64k program memory space ffff 0000 note: the single flash block address structure for doing as well as program rom flash. 1.2 data memory the sm79164 has 4k bytes on-chip ram, 256 bytes of it are the same as general 8052 internal memory structure while the expanded 3840 bytes on-chip ram can be accessed by external memory addressi ng method (by instruction movx), or by ?bank mapping direct addressing mode? as described in page 8. specifications subject to change with out notice,contact your sales represent atives for the most recent information. 7/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 ff 80 7f 00 ff 80 0eff 0000 higher 128 bytes (access by indirect addressing mode only) sfr (accessed by direct addressing mode only) lower 128 bytes (accessed by direct & indirect addressing mode) expanded 3840 bytes ram (accessed by direct external addressing mode, by instruction movx, or by bank mapping direct addressing mode) on-chip expanded ram address structure. 1.2.1 data memory - lower 128 byte ($00 to $7f, bank 0 & bank 1) data memory $00 to $ff is the same as 8052. the address $00 to $7f can be accessed by direct and indirect addressing modes. address $00 to $1f is register area. address $20 to $2f is memory bit area. address $30 to $7f is for general memory area. 1.2.2 data memory - hi gher 128 byte ($80 to $f f, bank 2 & bank 3) the address $80 to $ff can be accessed by indirect addressing mode or by bank mapping direct addressing mode. address $80 to $ff is data area. 1.2.3 data memory - expanded 3840 byt es ($0000 to $0eff, ba nk 4 ~ bank 63) from external address $0000 to $0eff is the on-chip expanded ram area, total 3840 bytes. this area can be accessed by external direct addressing mode (by instruction movx) or by bank mapping direct addressing mode as described below: 1.3 bank mapping di rect addressing mode : we provide ram bank address ?40h~7fh? as mapping window wh ich allow user access all the 4kb on-chip ram through this ram bank address. that means using direct addressing mode can access all the 4kb on-chip ram. please see next page for the mapping mode table. (ome = 1) specifications subject to change with out notice,contact your sales represent atives for the most recent information. 8/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 bs5 bs4 bs3 bs2 bs1 bs0 040h ~ 07fh mapping address note 0 0 0 0 0 0 000h ~ 03fh lower 128 byte ram 0 0 0 0 0 1 040h ~ 07fh lower 128 byte ram 0 0 0 0 1 0 080h ~ 0bfh higher 128 byte ram 0 0 0 0 1 1 0c0h ~ 0ffh higher 128 byte ram 0 0 0 1 0 0 0000h ~ 003fh on-chip expanded 3840 byte ram 0 0 0 1 0 1 0040h ~ 007fh ? 0 0 0 1 1 0 0080h ~ 00bfh ? 0 0 0 1 1 1 00c0h ~ 00ffh ? 0 0 1 0 0 0 0100h ~ 013fh ? 0 0 1 0 0 1 0140h ~ 017fh ? 0 0 1 0 1 0 0180h ~ 01bfh ? 0 0 1 0 1 1 01c0h ~ 01ffh ? 0 0 1 1 0 0 0200h ~ 023fh ? 0 0 1 1 0 1 0240h ~ 027fh ? 0 0 1 1 1 0 0280h ~ 02bfh ? 0 0 1 1 1 1 02c0h ~ 02ffh ? 0 1 0 0 0 0 0300h ~ 033fh ? 0 1 0 0 0 1 0340h ~ 037fh ? 0 1 0 0 1 0 0380h ~ 03bfh ? 0 1 0 0 1 1 03c0h ~ 03ffh ? 0 1 0 1 0 0 0400h ~ 043fh ? 0 1 0 1 0 1 0440h ~ 047fh ? 0 1 0 1 1 0 0480h ~ 04bfh ? 0 1 0 1 1 1 04c0h~04ffh ? 1 1 1 0 0 1 0d40h ~ 0d7fh ? 1 1 1 0 1 0 0d80h ~ 0dbfh ? 1 1 1 0 1 1 0dc0h ~ 0dffh ? 1 1 1 1 0 0 0e00h ~ 0e3fh ? 1 1 1 1 0 1 0e40h ~ 0e7fh ? 1 1 1 1 1 0 0e80h ~ 0ebfh ? 1 1 1 1 1 1 0ec0h ~ 0effh ? specifications subject to change with out notice,contact your sales represent atives for the most recent information. 9/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 with this bank mapping scheme, user can access entire 4k byte on-chip ram with direct addressing method. that means using the window area ($040~$07f), user can access any ban k (64 byte) data of 4k byte on-chip ram space which is selected by bs[5:0] of data bank control register (dbank, $86). for example, user write #30h to $101 address: mov dbank, #88h ; set bank mapping $040~$07f to $0100~$013f mov a, #30h ; store #30h to a mov 41h, a ; write #30h to $0101 address data bank control re gister (dbank, $86) data bank select enable bit bse = 1 enables the data bank select function data bank select enable bit bse = 0 disables the data bank select function bs[5:0] setting will map $040~$07f ram space to enti re 4k byte on-chip ram space. internal ram control register (rcon, $85) sm79164 has 3840 byte on-chip ram which can be accessed by external memory addressing method only. (by instruction movx). the address space of instruction movx @rn is determined by bit 3, bit2, bit1, bit 0 (rams3, rams2, rams1, rams0) of rcon. th e default setting of rams3, rams2, rams1, rams0 bits is 0000 (page0). bit-7 bit-0 bse unused bs5 bs4 bs3 bs2 bs1 bs0 read / write: r/w - r/w r/w r/w r/w r/w r/w reset value:0*000001 bit-7 bit-0 unused unused unused unused rams3 rams2 rams1 rams0 read / write:----r/wr/wr/wr/w reset value:**** 0000 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 10/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 the port 0, port2, port3.6 and port3.7 can be used as gener al purpose i/o pin while port 0 is open-drain structure. system control register (sconf, $bf) wdr : watch dog timer reset. ome : 3840 bytes on-chip ram enable bit alei : ale output in hibit bit, to reduce emi setting bit 0 (alei) of sconf can inhibit the cl ock signal in fosc/6hz output to the ale pin. the bit 1 (ome) of sconf can enable or disable the on-chip expanded 3840 byte ram. the default setting of ome bit is 0 (disable). the bit 7 (wdr) of sconf is watch dog time r reset bit. it will be set to 1 when reset signal generated by wdt overflow. user should check wdr bit whenever un-predicted reset happened. rams3 rams2 rams1 rams0 movx @ri i=0, 1 mapping to expended ram address 0 0 0 0 $0000 ~ $00ff 0 0 0 1 $0100 ~ $01ff 0 0 1 0 $0200 ~ $02ff 0 0 1 1 $0300 ~ $03ff 0 1 0 0 $0400 ~ $04ff 0 1 0 1 $0500 ~ $05ff 0 1 1 0 $0600 ~ $06ff 0 1 1 1 $0700 ~ $07ff 1 0 0 0 $0800 ~ $08ff 1 0 0 1 $0900 ~ $09ff 1 0 1 0 $0a00 ~ $0aff 1 0 1 1 $0b00 ~ $0bff 1 1 0 0 $0c00 ~ $0cff 1 1 0 1 $0d00 ~ $0dff 1 1 1 0 $0e00 ~ $0eff bit-7 bit-0 wdr unused unused unused unused unused ome alei read / write:r/w-----r/wr/w reset value:0*****00 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 11/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 1.4 i/o pin configuration the ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. each i/o pin can be used independently as an input or an output. for i/o ports to be used as an input pin, the port bit latch must contain a ?1? which turns off the output driver fet. then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can be pulled low by an external source. the port 0 has open-drain outputs which means its pull-ups are not active during normal port operation. writing ?1 ? to the port 0 bit latch will causi ng bit floating so that it can be used as a high-impedance input. the port 4 used as gpio will has the same function as port 1, 2 and 3. pin input data output data pin input data output data port 0 standard 8051 port 1, 2 and 3 standard 8051 2. port 4 for plcc or qfp package: the bit addressable port 4 is available with plcc or qfp package. the port 4 has only 4 pins and its port address is located at 0d8h. the function of port 4 is the same as the function of port 1, port 2 and port 3. port4 (p4, $d8) the bit 3, bit 2, bit 1, bit 0 output the setting to pin p4.3, p4.2 , p4.1, p4.0 respectively. 3. watch dog timer the watch dog timer (wdt) is a 16-bit free-running counter th at generate reset signal if the counter overflows. the wdt is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. the wdt function can help user software re cover from abnormal software condition. the wdt is different from timer0, timer1 and timer2 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. user should check wdr bit of scon f register whenever un-predicted reset happened. the purpose of the secure procedure is to prevent t he wdtc value from being changed when system runaway. there is a 250khz rc oscillator embedded in chip. set wdte = ?1? will enable the rc oscillator and the frequency is inde- pendent to the system frequency. to enable the wdt is done by setting 1 to the bit 7 (wdte) of wdtc. after wdte set to 1, the 16-bit counter starts to count with the rc oscillator. it will generate a re set signal when overflows. the wdte bi t will be cleared to 0 automatically when sm79164 been reset, either hardware reset or wdt reset. to reset the wdt is done by setting 1 to the clear bit of wd tc before the counter overflow. this will clear the content of the 16-bit counter and let the counter re-start to count from the beginning. bit-7 bit-0 unused unused unused unused p4.3 p4.2 p4.1 p4.0 read / write:----r/wr/wr/wr/w reset value:**** 1111 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 12/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 3.1 watch dog timer registers: watch dog timer registers - wdt control register (wdtc, $9f) wdte : watch dog timer enable bit clear : watch dog timer reset bit ps[2:0] : overflow period select bits watch dog key regist er - (wdtkey, $97h) by default, the wdtc is read only. user need to write valu es 1eh, e1h sequentially to the wdtkey($97h) register to enable the wdtc write attribute, that is mov wdtkey, # 1eh mov wdtkey, # e1h when wdtc is set, user need to write another values e1 h, 1eh sequentially to the wdtkey( $97h) register to disable the wdtc write attribute, that is mov wdtkey, # e1h mov wdtkey, # 1eh bit-7 bit-0 wdte reserve clear unused unused ps2 ps1 ps0 read / write: r/w - r/w - - r/w r/w r/w reset value: 0 * 0 * * 0 0 0 ps [2:0] overflow period (ms) 000 2.048 001 4.096 010 8.192 011 16.384 100 32.768 101 65.536 110 131.072 111 262.144 bit-7 bit-0 wdt key7 wdt key6 wdt key5 wdt key4 wdt key3 wdt key2 wdt key1 wdt key0 read / write: w w w w w w w w reset value: 0 0 0 0 0 0 0 0 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 13/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 watch dog timer register - system control register (sconf, $bf) the bit 7 (wdr) of sconf is watch dog timer reset bit. it will be set to 1 when re set signal gene rated by wdt overflow. user should check wdr bit whenever un-predicted reset happened 4. reduce emi function the sm79164 allows user to re duce the emi emission by setting 1 to the bit 0 (alei) of sconf register. this function will inhibit the clock signal in fosc/6hz output to the ale pin. 5. pulse width modulation (pwm) the pulse width modulation (pwm) module contains 1 kind of pwm sub module: pwm. pwm also has four 8-bit channels. 5.1 pwm function description: each pwm channel contains a 8-bit wide pwm data register (pwmdr) to decide number of continuous pulses within a pwm frame cycle. the value programmed in the register will determin e the pulse length of the output. the pwm channel can be configured as 5-bit or 8-bit resolution. if a channel is configured as 5-bit resolution, only lsb 5 bits are available. the value of each pwm data register (pwmdr) is continuously compared with the content of an internal counter to deter- mine the state of each pwm channel output pin. 5.2 pwm registers - p1con[7: 0], pwmc[7:0], pwmd[7:0] pwm registers - port1 configur ation register (p1con, $9b) pwm[7:0]e: when the bit set to one, the corresponding pwm pin is active as pwm function. when the bit reset to zero, the corresponding pwm pin is active as i/o pin. five bits are cleared upon reset. pwm registers - pwm control register (pwmc[7:0], $de ~ $db, $d6 ~ $d3) bit-7 bit-0 wdr unused unused unused unused unused ome alei read / write:r/w-----r/wr/w reset value:0*****00 pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 read / write: r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 bit-7 bit-0 unused unused unused unused unus ed pbs[7:0] pfs[7:0]1 pfs[7:0]0 read / write: - - - - - r/w r/w r/w reset value:*****00 0 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 14/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 pfs[7:0][1:0] : these two bits is 2?s po wer parameter to form a frequency divider for input clock. pbs[7:0] : this bit decides channel bit resolution. if pbs[7:0] is set, the ch annel is 5-bit resolution. note : if x?tal > 24mhz, can not select pfs[1:0] = 00 pwm registers - pwm data register (pwmd[7:0], $be ~ $bb, $b6 ~ $b3) pwm[7:0][7:0] : content of pwm data regist er. if pbs[7:0] is set, only pwm[7:0][4:0] ar e available.] pfs[7:0]1 pfs[7:0]0 divider pwm clock, fosc=12mhz pwm clock, fosc=24mhz 0 0 0.5 24mhz (note) 48mhz (note) 0 1 1 12mhz 24mhz 102 6mhz 12mhz 114 3khz 6mhz bit-7 bit-0 pwmd [7:0]7 pwmd [7:0]6 pwmd [7:0]5 pwmd [7:0]4 pwmd [7:0]3 pwmd [7:0]2 pwmd [7:0]1 pwmd [7:0]0 read / write: r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 15/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 example of pwm timing diagram: for 5-bit resolution channel, m = content of pwmd[7:0]: m = $00 m = $01 m = $0f m = $1f pwm clock frequency = 1/t = fosc / divider the pwm output cycle frame frequency = pwm clock frequency / 32 for 8-bit resolution channel: m = $00 m = $01 m = $7f m = $ff pwm clock frequency = 1/t = fosc / divider the pwm output cycle frame frequency = pwm clock frequency / 256 32t 256t specifications subject to change with out notice,contact your sales represent atives for the most recent information. 16/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 operating conditions note1:operating voltage {v=2.4v ~ 3.0v, l=3.0v ~ 3.6v, c=4.5v ~ 5.5v} note2:working frequency {v=16mhz for j/q package,l=20mhz for p package,l=25mhz for j/q package,c=25mhz for p package,c=35mhz for j/q package} symbol description min. typ. max. unit. remarks ta operating temperature -40 25 85 o c ambient temperature under bias vcc supply voltage 2.4 - 5.5 v note1 fosc35 oscillator frequency 3.0 - 35 mhz note2 (ta = -40 degree c to 85 degree c, vcc = 2.4v to 5.5v) symbol parameter valid vil1 input low voltage port 0,1,2,3,4,#ea vil2 input low voltage res, xtal1 vih1 input high volt age port 0,1,2,3,4,#ea vih2 input high voltage res, xtal1 vol1 output low volt age port 0, ale, #psen vol2 output low voltage port 1,2,3,4 voh1 output high voltage port 0 voh2 output high volta ge port 1,2,3,4,ale,#psen iil logical 0 input current port 1,2,3,4 itl logical transition current port 1,2,3,4 ili input leakage current port 0, #ea r res reset pulldown resistance res c io pin capacitance i cc power supply current vdd dc characteristics + min. max. unit test conditions -0.5 0 2.0 70%vcc 2.4 90%vcc 50 2.4 90%vcc 0.8 0.8 vcc+0.5 vcc+0.5 0.45 0.45 -75 -650 10 300 10 20 6.5 50 v v v v v v v v v v ua ua ua kohm pf ma ma ua iol=3.2ma iol=1.6ma ioh=-800ua (only for vcc=5v) ioh=-80ua ioh=-60ua (only for vcc=5v) ioh=-10ua vin=0.45v vin=2.0v 0.45v specifications subject to change with out notice,contact your sales represent atives for the most recent information. 18/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 application reference note: oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or cerami c resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacturer for appropriate value of external components. xi x2 sm79164 x'tal r c1 c2 data memory read cycle timing osc t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 ale #psen #rd port2 port0 address a15 - a8 inst in float a7 - a0 float data in float address or float note: oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or cerami c resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacturer for appropriate value of external components. xi x2 sm79164 x'tal r c1 c2 x'tal 3mhz 6mhz 9mhz 12mhz c1 30 pf 30 pf 30 pf 30 pf c2 30 pf 30 pf 30 pf 30 pf r open open open open x'tal 16mhz 25mhz 33mhz c1 30 pf 15 pf 5 pf c2 30 pf 15 pf 5 pf r open 62k 6.8k valid for sm79164 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 19/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 osc ale #psen #rd,#wr port2 port0 t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 address a15 - a8 address a15 - a8 float a7 - a0 float inst in float a7 - a0 float inst in float program memory read cycle timing data memory write cycle timing osc t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t1 t2 ale #psen #wr port2 port0 address a15 - a8 inst float a7 - a0 data out address or float t12 t3 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 20/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 i/o ports timing t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 t4 t5 t6 t7 t8 inputs p0,p1 sampled sampled inputs p2,p3 output by mov px,src rxd at serial port shift clock (mode 0) current data next data sampled x1 timing critical, requirement of exte rnal clock (vss=0.0v is assumed) vdd-0.5v 0.45v 70%vdd 20%vdd-0.1v tchcl tclcl tchcx tclch tclcx tm.i external program memory read cycle #psen ale port 0 port 2 tplph tlhll tllpl tavll tllax tpxix tpxiz taviv tplaz tpliv a0 - a7 instruction. in a0 - a7 a8 - a15 a8 - a15 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 21/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 tm.ii external data memory read cycle #psen ale #rd port 0 port 2 tyhlh tlldv tllyl trlrh tavll tllax trlaz tavyl tavdv p2.0 - p2.7 or a8 - a15 from dph trhdz trhdx a0 - a7 from ri or dpl data in a0 - a7 from pcl instrl in a8 - a15 from pch trldv tm.iii external da ta memory write cycle #psen ale #wr port 0 port 2 tlhll tyhlh tavll tllax tqvwx tllyl tavyl twlwh twhqx tqvwh a0-a7 from pcl instrl in p2.0-p2.7 or a8-a15 from dph a8-a15 from pch a0-a7 from ri or dpl data out specifications subject to change with out notice,contact your sales represent atives for the most recent information. 22/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 pdip 40l (600mil) package informatio n note: 1. refer to jedec std.m s-011(ac). 2. d im ension d and e1 do not include m old protrusion. allowable protrusion is 0.25 mm per side. d and e1 are maximum plastic body size dimension include mold mismatch. 3. dimension b3 does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.2mm . d im ension in m m d im ension in m il symbol min nom max min nom max a1 0.254 10 a2 3.683 3.810 3.937 145 150 155 b 0.356 0.500 0.660 14 20 26 b1 0.356 0.457 0.508 14 18 22 b2 1.016 1.270 1.524 40 50 60 b3 1.016 1.321 1.626 40 52 64 c 0.203 0.254 0.432 8 10 17 c1 0.203 0.254 0.356 8 10 14 d 52.07 52.2 52.32 2050 2055 2060 e 14.99 15.24 15.49 590 600 610 e1 13.69 13.87 13.94 539 546 549 e 2.540 100 eb 15.75 16.26 16.76 620 640 660 l 2.921 3.302 3.683 115 130 145 s 1.727 1.981 2.235 68 78 88 q1 1.651 1.778 1.905 65 70 75 0 10 0 10 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 23/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 plcc 44l package informatio n unit symbol inch(ref) mm(base) a 0.180(max) 4.572(max) a1 0.024 0.005 0.52 0.14 a2 0.105 0.005 2.667 0.127 b 0.018 + 0.004 - 0.002 0.457 + 0.102 - 0.051 b1 0.028 + 0.004 - 0.002 0.711 + 0.102 - 0.051 c 0.010(typ) 0.254(typ) d 0.690 0.010 17.526 0.254 d1 0.653 0.003 16.586 0.076 d2 0.610 0.020 15.494 0.508 e 0.690 0.010 17.526 0.254 e1 0.653 0.003 16.586 0.076 e2 0.610 0.010 15.494 0.254 e 0.050(typ) 1.270(typ) y 0.003(max) 0.076(max) 0~5 0~5 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 24/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 q fp 44l(10x10x2.0m m ) package inform atio n note: 1. refer to jedc std.ms-022(ab). 2. dimension e1 do not include mold protrusion. allowable protrusion is 0.25mm per side.e1 are maximum plastic body size dimension include mold mismatch . 3. dimension b does not include dambar protrusion .allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.1 mm. dimension in mm dimension in mil symbol min nom max min nom max a 2.45 964 a1 0.05 0.15 0.25 2.1 6.0 9.6 a2 1.90 2.00 2.10 74.8 78.7 82.7 b 0.29 0.32 0.45 11.4 12.6 17.7 b1 0.29 0.30 0.41 11.4 11.8 16.1 c 0.11 0.17 0.23 4.3 6.7 9.1 c1 0.11 0.15 0.19 4.3 5.9 7.5 e 13.00 13.20 13.40 512 520 528 e1 9.90 10.00 10.10 390 394 398 e 0.800 31.5 l 0.73 0.88 1.03 28.7 34.6 40.6 l1 1.50 1.60 1.70 59.1 63.0 66.9 y 0.076 3 0 7 0 7 specifications subject to change with out notice,contact your sales represent atives for the most recent information. 25/26 ver 2.1 sm79164 08/2006 syncmos technologies international. inc. sm79164 company contact info programmer model number advantech 7f, no.98, ming-chung rd., shin-tien city, taipei, taiwan, roc web site: http://www.aec.com.tw tel:02-22182325 fax:02-22182435 e-mail: aecwebmaster@advantech.com.tw labtool - 48 (1 * 1) labtool - 848 (1*8) caprilion p.o. box 461 kaohsiung, taiwan, roc web site: http://www.market.net.tw/ ~ cap/ tel:07-3865061 fax:07-3865421 e-mail: cap@market.net.tw univ2000 hi-lo 4f, no. 20, 22, ln, 76, rui guang rd., nei hu, taipei, taiwan, roc. web site: http://www.h ilosystems.com.tw tel:02-87923301 fax:02-87923285 e-mail: support@hilosystems.com.tw all - 11 (1*1) gang - 08 (1*8) leap 6th f1-4, lane 609, chunghsin rd., sec. 5, sanchung, taipei hsien, taiwan, roc web site: http://www.leap.com.tw tel:02-29991860 fax:02-29990015 e-mail: service@leap.com.tw chipstation (1*1) su - 2000 (1*8) xeltek electronic co., ltd 338 hongwu road, nanjing, china 210002 web site: http://www.xeltek-cn.com tel:+86-25-4408399, 4543153-206 e-mail: xelclw@jlonline.com, xelgbw@jlonline.com superpro/2000 (1*1) superpro/680 (1*1) superpro/280 (1*1) superpro/l+(1*1) emcu writer list |
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